Difference between revisions of "Led Matrix 32x64"

Revision as of 21:12, 4 September 2011

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-[[Category:Ongoing_Projects]]
-A FPGA-based interface controller for
-[http://www.limpkin.fr/index.php?post/2011/05/12/Oops...-I-dit-it-again%21 Limpkin's RGB LED matrices].
 === Matrix reference ===
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 * price: ~ 150.- USD
+== Pictures ==
-== Overview ==
+[[File:DSCN5181.JPG]]
-* FPGA drives 1 or more (up to 4?) matrices
-* use block ram or external SRAM for frame buffer storage
-* interface with PC
-=== Feature ideas ===
-* double buffering
-* larger off-screen buffer + compositing ops?
-* character generation
-* update only sections
-* small CPU core to execute short programs?
-== Components ==
-=== Memory ===
-External SRAM needs to be fast enough to handle all reads during one
-cycle.  Per connected matrix we need to read 6 bytes per cycle.
-Clearly this would require use to run at 150MHz, which is infeasible.
-If we use a separate chip per matrix block (6 chips or 3 chips with
-bit width), we can still operate with 25MHz.
-Concurrent writes need to be possible, but at a lower speed.  Either
-buffer reads and slip in writes when there is slack (complicated), or
-alternate between reads and writes at higher speed (DDR?).