[[Category:Ongoing_Projects]]
A FPGA-based interface controller for
[http://www.limpkin.fr/index.php?post/2011/05/12/Oops...-I-dit-it-again%21 Limpkin's RGB LED matrices].
=== Matrix reference ===
* sizeSize: 64x32 32x64 RGB LEDs(127x256mm)* organizationOrganization: 2 blocks (upper and lower) with each 16 lines à of 64 LEDs
* (6) 64 bit shift registers
* input pins:** R, G, B for each upper and lower: R1, G1, B1, R2, G2, B2; 1 40ns period = LED on25MHz max.** clock (next bit, rising edge)~4A with full matrix in white color** latch (latch shifted data to output, rising edge)** enable (drives LEDs from latched data?, 0 = enable)** 5V signals*Serial MCU Interface* 40ns period = 25MHz maxPrice: ~ 150.- USD
== Overview ==
* FPGA drives === Input pins ===# '''DR1''' - RED for lines 1 or more -16 (up to 4?1 = LED on) matrices* use block ram or external SRAM # '''DG1''' - GREEN for frame buffer storagelines 1-16 (1 = LED on)# '''DB1''' - BLUE for lines 1-16 (1 = LED on)# '''GND''' - Ground Reference# '''DR2''' - RED for lines 17-32 (1 = LED on)# '''DG2''' - GREEN for lines 17-32 (1 = LED on)# '''DB2''' - BLUE for lines 17-32 (1 = LED on)# '''GND''' - Ground Reference# '''A''' - Used for the bit selection of one of 16 rows# '''B''' - Used for the bit selection of one of 16 rows# '''C''' - Used for the bit selection of one of 16 rows# '''D''' - Used for the bit selection of one of 16 rows# '''CLK''' - Clock imput for 74HC595 shift register# '''LAT''' - Content of 74HC595 Shift Register transferred to output latches# '''EN''' - Enable 74HC138 encoder to set one of 16 rows (0 = enable)* interface with PC# '''GND''' Ground Reference
=== Feature ideas ===
* double buffering=== Pictures ===* larger off-screen buffer + compositing ops?[[File:Ledmatrix_1.JPG||500px]]* character generation* update only sections* small CPU core to execute short programs?[[File:Ledmatrix_2.JPG||500px]]