Difference between revisions of "Led Matrix 32x64"
From Fixme.ch
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− | == | + | A FPGA-based interface controller for |
+ | [http://www.limpkin.fr/index.php?post/2011/05/12/Oops...-I-dit-it-again%21 Limpkin's RGB LED matrices]. | ||
+ | |||
+ | |||
+ | === Matrix reference === | ||
+ | |||
+ | * size: 64x32 RGB LEDs | ||
+ | * organization: 2 blocks (upper and lower) with each 16 lines à 64 LEDs | ||
+ | * (6) 64 bit shift registers | ||
+ | * input pins: | ||
+ | ** R, G, B for each upper and lower: R1, G1, B1, R2, G2, B2; 1 = LED on | ||
+ | ** clock (next bit, rising edge) | ||
+ | ** latch (latch shifted data to output, rising edge) | ||
+ | ** enable (drives LEDs from latched data?, 0 = enable) | ||
+ | ** 5V signals | ||
+ | ** 40ns period = 25MHz max. | ||
+ | |||
+ | |||
+ | == Overview == | ||
+ | |||
+ | * FPGA drives 1 or more (up to 4?) matrices | ||
+ | * use block ram or external SRAM for frame buffer storage | ||
+ | * interface with PC | ||
+ | |||
+ | |||
+ | === Feature ideas === | ||
+ | |||
+ | * double buffering | ||
+ | * larger off-screen buffer + compositing ops? | ||
+ | * character generation | ||
+ | * update only sections | ||
+ | * small CPU core to execute short programs? |
Revision as of 11:49, 1 August 2011
A FPGA-based interface controller for
Limpkin's RGB LED matrices.
Matrix reference
- size: 64x32 RGB LEDs
- organization: 2 blocks (upper and lower) with each 16 lines à 64 LEDs
- (6) 64 bit shift registers
- input pins:
- R, G, B for each upper and lower: R1, G1, B1, R2, G2, B2; 1 = LED on
- clock (next bit, rising edge)
- latch (latch shifted data to output, rising edge)
- enable (drives LEDs from latched data?, 0 = enable)
- 5V signals
- 40ns period = 25MHz max.
Overview
- FPGA drives 1 or more (up to 4?) matrices
- use block ram or external SRAM for frame buffer storage
- interface with PC
Feature ideas
- double buffering
- larger off-screen buffer + compositing ops?
- character generation
- update only sections
- small CPU core to execute short programs?