Difference between revisions of "FixmeBus"
From Fixme.ch
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+ | __TOC__ | ||
__TOC__ | __TOC__ | ||
==Introduction== | ==Introduction== | ||
+ | FixmeBus is a field bus based on the half duplex RS485 famous hardware protocol. It is a master / slave architecture, with every slave chained together. The communication protocol has following parameters: | ||
+ | |||
+ | *38,400 bauds | ||
+ | *8 data bits | ||
+ | *1 start and 1 stop bit | ||
+ | *no parity | ||
+ | *no flow control | ||
+ | |||
+ | Each end of the bus is terminated with a 1% 120R resistor. | ||
+ | |||
+ | Every data frame on the bus is like this (byte on the left = first byte): | ||
+ | |||
+ | *2 bytes of slave adress (ID_HIGH and ID_LOW) => 65536 slave adress | ||
+ | **ID = 0 => Master | ||
+ | **ID = 65535 => order to all slaves (no ack) | ||
+ | **ID = 65000 to 65499 => order to a group of slave (no ack) | ||
+ | **ID = 1000 to 64999 => order to an unique slave (ack) | ||
+ | *2 bytes for the function (FCT_HIGH and FCT_LOW) | ||
+ | *1 byte for the number of data bytes to transmit (N_BYTE) | ||
+ | *n byte(s) of data (DATA) bytes (max. 200 bytes per frame) | ||
+ | *2 bytes for the CRC (CRC_HIGH and CRC_LOW) | ||
+ | |||
+ | {| class="wikitable" style="text-align: center; color: green;" | ||
+ | |b0 | ||
+ | |b1 | ||
+ | |b2 | ||
+ | |b3 | ||
+ | |b4 | ||
+ | |b5 | ||
+ | |... | ||
+ | |bn+4 | ||
+ | |bn+5 | ||
+ | |bn+6 | ||
+ | |- | ||
+ | !ID_HIGH | ||
+ | !ID_LOW | ||
+ | !FCT_HIGH | ||
+ | !FCT_LOW | ||
+ | !N_BYTE | ||
+ | !DATA[0] | ||
+ | !... | ||
+ | !DATA[n-1] | ||
+ | !CRC_HIGH | ||
+ | !CRC_LOW | ||
+ | |} | ||
==Technical information== | ==Technical information== | ||
#[[Hardware]] | #[[Hardware]] | ||
#[[Software]] | #[[Software]] |
Revision as of 23:04, 12 April 2014
Contents
Introduction
FixmeBus is a field bus based on the half duplex RS485 famous hardware protocol. It is a master / slave architecture, with every slave chained together. The communication protocol has following parameters:
- 38,400 bauds
- 8 data bits
- 1 start and 1 stop bit
- no parity
- no flow control
Each end of the bus is terminated with a 1% 120R resistor.
Every data frame on the bus is like this (byte on the left = first byte):
- 2 bytes of slave adress (ID_HIGH and ID_LOW) => 65536 slave adress
- ID = 0 => Master
- ID = 65535 => order to all slaves (no ack)
- ID = 65000 to 65499 => order to a group of slave (no ack)
- ID = 1000 to 64999 => order to an unique slave (ack)
- 2 bytes for the function (FCT_HIGH and FCT_LOW)
- 1 byte for the number of data bytes to transmit (N_BYTE)
- n byte(s) of data (DATA) bytes (max. 200 bytes per frame)
- 2 bytes for the CRC (CRC_HIGH and CRC_LOW)
b0 | b1 | b2 | b3 | b4 | b5 | ... | bn+4 | bn+5 | bn+6 |
ID_HIGH | ID_LOW | FCT_HIGH | FCT_LOW | N_BYTE | DATA[0] | ... | DATA[n-1] | CRC_HIGH | CRC_LOW |
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