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Langage VHDL

No change in size, 17:20, 2 January 2018
/* CADENAS V0.3 - DONE */
''In English :''With an electronics board created by the ETML-ES School and equiped with a FPGA(EMP1270T144C5), realization program in VHDL which allows to simulate the behavior of a padlock. 2 switches are used to 3 modes : rest / recording the new code / reading. 4 switches allow to record a new code or to read the code
* [FAITDONE] Realization with one process (case) of the display part, management leds, management code* [FAITDONE] Simulation * [FAITDONE] Programming the board
== Project Source ==
939
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