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Langage VHDL

969 bytes added, 16:53, 27 December 2016
/* Description Project */
* [DONE] Realized a cycle counter of 2Hz to do turned the segments in clockwise (Way: F1 -> E1 -> A1 -> A2 -> B2 -> C1... it is continuous
* [DONE] With a push (> 1s) on the S9 Switch, the cycle must stopped if after a new push on this button, the cycle must be the opposite at the first, if a new push again the cylce must stopped and to finish if still a push, the cycle set out again at the start cycle.
 
=== 7 Segment Display - DONE ===
''IN FRENCH'' A l'aide d'une FPGA (EMP1270T144C5) et d'une carte électronique créée par l'ETML-ES, réalisation / simulation d'un message défilant à l'aide deux affichage 7 segments à disposition.
* [FAIT] lire un tableau contenant un message et le faire afficher sur les deux affichage A & B
* [FAIT] La valeur du segment B se déplacera sur le segment A, la valeur sur le segment disparaitra
* [FAIT] le déplacement du message sera de 500ms (2Hz)
 
''In English :'' With an electronics board created by the ETML-ES School and equiped with a FPGA, realization / Simulation of the VHDL code which allows to read a table and to display a message on two 7 Segments Display
* [DONE] read a table including a message and to display this message on two 7 Segments Display
* [DONE] the Segment value (B) will moving on the segment B -> and the Segment value A will dispear
* [DONE] the message moving will be of 500ms (2Hz)
== Project Source ==
939
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