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Led Matrix 32x64

329 bytes removed, 21:13, 4 September 2011
[[Category:Ongoing_Projects]]
 
A FPGA-based interface controller for
[http://www.limpkin.fr/index.php?post/2011/05/12/Oops...-I-dit-it-again%21 Limpkin's RGB LED matrices].
 
 
=== Matrix reference ===
* sizeSize: 64x32 32x64 RGB LEDs(127x256mm)* organizationOrganization: 2 blocks (upper and lower) with each 16 lines à of 64 LEDs
* (6) 64 bit shift registers
* input pins:** R, G, B for each upper and lower: R1, G1, B1, R2, G2, B2; 1 = LED on** clock (next bit, rising edge)** latch (latch shifted data to output, rising edge)** enable (drives LEDs from latched data?, 0 = enable)** 5V signals** 40ns period = 25MHz max.
* ~4A with full matrix in white color
* price5V signals* Serial MCU Interface* Price: ~ 150.- USD  == Overview == * FPGA drives 1 or more (up to 4?) matrices* use block ram or external SRAM for frame buffer storage* interface with PC 
=== Feature ideas ===
* double buffering
* larger off-screen buffer + compositing ops?
* character generation
* update only sections
* small CPU core to execute short programs?
== Components =Input pins ===# '''DR1''' - RED for lines 1-16 (1 = LED on)# '''DG1''' - GREEN for lines 1-16 (1 = LED on)# '''DB1''' - BLUE for lines 1-16 (1 = LED on)# '''GND''' - Ground Reference# '''DR2''' - RED for lines 17-32 (1 = LED on)# '''DG2''' - GREEN for lines 17-32 (1 = LED on)# '''DB2''' - BLUE for lines 17-32 (1 = LED on)# '''GND''' - Ground Reference# '''A''' - Used for the bit selection of one of 16 rows# '''B''' - Used for the bit selection of one of 16 rows# '''C''' - Used for the bit selection of one of 16 rows# '''D''' - Used for the bit selection of one of 16 rows# '''CLK''' - Clock imput for 74HC595 shift register# '''LAT''' - Content of 74HC595 Shift Register transferred to output latches# '''EN''' - Enable 74HC138 encoder to set one of 16 rows (0 = enable)# '''GND''' Ground Reference
=== Memory ===
External SRAM needs to be fast enough to handle all reads during one
cycle. Per connected matrix we need to read 6 bytes per cycle.
Clearly this would require use to run at 150MHz, which is infeasible.
If we use a separate chip per matrix block (6 chips or 3 chips with
16bit width), we can still operate with 25MHz.
Concurrent writes need to be possible, but at a lower speed. Either=== Pictures ===buffer reads and slip in writes when there is slack (complicated), or[[File:Ledmatrix_1.JPG||500px]]alternate between reads and writes at higher speed (DDR?)[[File:Ledmatrix_2.JPG||500px]]
Freestorm
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