Changes
=== Matrix reference ===
* price: ~ 150.- USD
== Overview Pictures == * FPGA drives 1 or more (up to 4?) matrices* use block ram or external SRAM for frame buffer storage* interface with PC === Feature ideas === * double buffering* larger off-screen buffer + compositing ops?* character generation* update only sections* small CPU core to execute short programs? == Components == === Memory === External SRAM needs to be fast enough to handle all reads during onecycle. Per connected matrix we need to read 6 bytes per cycle.Clearly this would require use to run at 150MHz, which is infeasible.If we use a separate chip per matrix block (6 chips or 3 chips with16bit width), we can still operate with 25MHz. Concurrent writes need to be possible, but at a lower speed. Eitherbuffer reads and slip in writes when there is slack (complicated), oralternate between reads and writes at higher speed (DDR?)[[File:DSCN5181.JPG]]
