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Langage VHDL

455 bytes added, 15:18, 13 September 2016
/* entity */
''IN ENGLISH'': then a entity must been implemented, this one includes the ports (input/output) either real or linked a the electronic internal componant
 
==== PORTS ====
''IN FRENCH'': Pour déclarer un port, il faut : UN '''NOM''', UN '''MODE''' (in / out / inout), UN '''TYPE''' (bit / std_logic / bit_vector / std_logic_vector)
 
''IN ENGLISH'': To declare a port, it must : a '''NOM''', a '''MODE''' (in / out / inout), a '''TYPE''' (bit / std_logic / bit_vector / std_logic_vector)
entity NOM_ENTITY is
port( -- délcaration ports IN/OUT exemple_1 : in bit; exemple_2 : out std_logic; exemple_3 : inout std_logic_vector(3 downto 0) );
end NOM_ENTITY;
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