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Langage VHDL

1 byte added, 15:19, 13 September 2016
/* PORTS */
''IN FRENCH'': Pour déclarer un port, il faut : UN '''NOM''', UN '''MODE''' (in / out / inout), UN '''TYPE''' (bit / std_logic / bit_vector / std_logic_vector)
''IN ENGLISH'': To declare a port, it must : a '''NOMNAME''', a '''MODE''' (in / out / inout), a '''TYPE''' (bit / std_logic / bit_vector / std_logic_vector)
entity NOM_ENTITY is
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