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Langage VHDL

7 bytes added, 11:39, 27 June 2016
/* architecture */
''IN ENGLISH'' : the architecture is the program body, this one makes up of internal signal's declaration not used in the entity. Then use the key word '''begin''' follow-up of program's behavior // allocation // '''process''' statment.
exemple <u>Exemple</u>
architecture Architecture_name of Entity_name is
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