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Langage VHDL

11 bytes removed, 09:37, 28 July 2016
/* 7 Segment Display */
* [FAIT] réalisation du schéma logique sous Quatrus
* [FAIT] Simulation avec Quartus
* [EN COURSFAIT] Réalisation d'un code VHDL selon les équations trouvé avec les tables de Karnaugh
''In English :'' With an electronics board created by the ETML-ES School and equiped with a FPGA, realization of logic schemtatics concerning the 7 Segments dispaly (0 to F) under Quartus and to write a VHDL Code.
* [DONE] Realization of logic schematics (Quartus)
* [DONE] Simulation with Quartus
* [IN PROGRESSDONE] realization VHDL code according the Karnaugh Table
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